1) What is PCI Express® (PCIe) 3.0? What are the requirements for this evolution of the PCIe® architecture??
PCIe 3.0 is the next evolution of the ubiquitous, general-purpose PCI Express I/O standard. At a bit rate of 8GT/s, the interconnect throughput bandwidth is doubled over PCIe 2.0, while maintaining compatibility with software and mechanical interfaces. The key requirement for the evolution of the PCIe architecture is to continue to deliver performance scaling consistent with the bandwidth demands of major applications with low cost, low power, and minimal platform-level disruption.
One of the main factors in the wide adoption of the PCIe architecture is its sensitivity to high-volume manufacturing tolerances and materials, such as FR4 boards, low-cost clock supplies, connectors, etc. By providing full compatibility, the same topologies and channel scope as PCIe 2.0 will be supported for client and server configurations. Another important requirement is the ability to manufacture products using the most widely available silicon processing technology. For PCIe 3.0 architecture, PCI-SIG believes that a 65nm or higher process will be required to optimize silicon area and power.
2) What is the bitrate for PCIe 3.0 and how does it compare to previous generations of PCIe?
The bitrate for PCIe 3.0 is 8GT/s. This bit rate represents the best compromise between manufacturability, cost, power, and compatibility. The PCI-SIG analysis covered multiple topologies and configurations, including servers. All of these studies confirmed the feasibility of 8GT/s signaling with low-cost enablers and with minimal increases in power and silicon chip size.
3) How does PCIe 3.0 8GT/s “double” the bitrate of PCIe 2.0 5GT/s?
The PCIe 2.0 bitrate is specified at 5GT/s, but with the 20 percent performance overhead of the 8b/10b encoding scheme, the delivered bandwidth is actually 4 Gb/s. PCIe 3.0 removes the 8b/10b encoding requirement and uses a more efficient 128b/130b encoding scheme instead. By removing this overhead, interconnect bandwidth can be doubled to 8 Gb/s with the implementation of the PCIe 3.0 specification. This bandwidth is the same as an interconnect running at 10GT/s with the 8b/10b coding overhead. In this way, PCIe 3.0 specifications provide the same effective bandwidth, but without the prohibitive penalties associated with 10GT/s signaling, such as PHY design complexity and increased silicon chip size and power.
4) Does this mean PCIe is terminated at 8GT/s? What comes next?
PCI-SIG will study its members and industry requirements for the next generation of PCIe architecture following the successful release of the PCIe 3.0 specifications. The highest signaling rates depend on a number of factors. The PCI-SIG is committed to delivering the most robust, high-performance I/O interconnect specifications while maintaining an unwavering focus on low-cost, low-power, high-performance manufacturability and compatibility. volume, taking advantage of advances in signaling. silicon process technologies and capabilities.
5) Will the PCIe 3.0 specs only offer an increase in signaling rate?
The PCIe 3.0 specifications will include the card and base electromechanical (EMC) specifications. There may be updates to other form factor specifications as the need arises. Within the Base specification, which defines a chip-to-chip interface, updates will be made to the electrical section to understand 8GT/s signaling. As the technology definition progresses through the PCI-SIG specification development process, additional ECNs and errata will be incorporated with each revision cycle. For example, current PCIe protocol extensions that address interconnect latency and other platform resource usage considerations will be incorporated into PCIe 3.0 specification revisions as they become available. The final PCIe 3.0 specification will consolidate all ECN and errata published since the release of the PCIe 2.1 specification, as well as interim errata.
